JPS60241346A - リング型ネツトワ−クによる記憶システム - Google Patents

リング型ネツトワ−クによる記憶システム

Info

Publication number
JPS60241346A
JPS60241346A JP9823084A JP9823084A JPS60241346A JP S60241346 A JPS60241346 A JP S60241346A JP 9823084 A JP9823084 A JP 9823084A JP 9823084 A JP9823084 A JP 9823084A JP S60241346 A JPS60241346 A JP S60241346A
Authority
JP
Japan
Prior art keywords
memory
data
buffer
buffers
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9823084A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0323026B2 (en]
Inventor
Akira Jinzaki
明 陣崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9823084A priority Critical patent/JPS60241346A/ja
Publication of JPS60241346A publication Critical patent/JPS60241346A/ja
Publication of JPH0323026B2 publication Critical patent/JPH0323026B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
JP9823084A 1984-05-16 1984-05-16 リング型ネツトワ−クによる記憶システム Granted JPS60241346A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9823084A JPS60241346A (ja) 1984-05-16 1984-05-16 リング型ネツトワ−クによる記憶システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9823084A JPS60241346A (ja) 1984-05-16 1984-05-16 リング型ネツトワ−クによる記憶システム

Publications (2)

Publication Number Publication Date
JPS60241346A true JPS60241346A (ja) 1985-11-30
JPH0323026B2 JPH0323026B2 (en]) 1991-03-28

Family

ID=14214157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9823084A Granted JPS60241346A (ja) 1984-05-16 1984-05-16 リング型ネツトワ−クによる記憶システム

Country Status (1)

Country Link
JP (1) JPS60241346A (en])

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012504285A (ja) * 2008-09-29 2012-02-16 タジツ トランスファー リミテッド ライアビリティ カンパニー ジオロケーション支援データ転送記憶
JP2012180531A (ja) * 1998-08-06 2012-09-20 Omlidon Technologies Llc 溶融加工性ポリ（テトラフルオロエチレン）
US8909738B2 (en) 2008-03-20 2014-12-09 Tajitshu Transfer Limited Liability Company Redundant data forwarding storage
US9203928B2 (en) 2008-03-20 2015-12-01 Callahan Cellular L.L.C. Data storage and retrieval

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012180531A (ja) * 1998-08-06 2012-09-20 Omlidon Technologies Llc 溶融加工性ポリ（テトラフルオロエチレン）
US8909738B2 (en) 2008-03-20 2014-12-09 Tajitshu Transfer Limited Liability Company Redundant data forwarding storage
US9203928B2 (en) 2008-03-20 2015-12-01 Callahan Cellular L.L.C. Data storage and retrieval
US9961144B2 (en) 2008-03-20 2018-05-01 Callahan Cellular L.L.C. Data storage and retrieval
JP2012504285A (ja) * 2008-09-29 2012-02-16 タジツ トランスファー リミテッド ライアビリティ カンパニー ジオロケーション支援データ転送記憶

Also Published As

Publication number Publication date
JPH0323026B2 (en]) 1991-03-28

Similar Documents

Publication Publication Date Title
US6874053B2 (en) Shared memory multiprocessor performing cache coherence control and node controller therefor
US6032179A (en) Computer system with a network interface which multiplexes a set of registers among several transmit and receive queues
US5014187A (en) Adapting device for accommodating different memory and bus formats
EP0126976B1 (en) Multiprocessor system with communicating random access shared memory
JP4046943B2 (ja) マルチポート内部キャッシュｄｒａｍ
EP0486167A2 (en) Multiple computer system with combiner/memory interconnection system
AU599534B2 (en) A diagnostic system in a data processing system
US4646237A (en) Data handling system for handling data transfers between a cache memory and a main memory
JPH0158540B2 (en])
JPH09251437A (ja) 計算機装置及び連続データサーバ装置
US5687393A (en) System for controlling responses to requests over a data bus between a plurality of master controllers and a slave storage controller by inserting control characters
US5260937A (en) Power conserving technique for a communications terminal time slot interchanger
US5895496A (en) System for an method of efficiently controlling memory accesses in a multiprocessor computer system
JPS60241346A (ja) リング型ネツトワ−クによる記憶システム
US8447952B2 (en) Method for controlling access to regions of a memory from a plurality of processes and a communication module having a message memory for implementing the method
JPH10262272A (ja) 時分割多重化通信媒体の簡単なインターフェース
EP0067519B1 (en) Telecommunications system
US5701431A (en) Method and system for randomly selecting a cache set for cache fill operations
EP0067294B1 (en) Data processing apparatus with master/slave control
US4618946A (en) Dual page memory system having storage elements which are selectively swapped between the pages
USRE38514E1 (en) System for and method of efficiently controlling memory accesses in a multiprocessor computer system
KR100215571B1 (ko) 전전자 교환기의 데이터 백업방법
US5710944A (en) Memory system and data communications system
SU1265780A1 (ru) Устройство дл сопр жени ЦВМ и накопител информации
JP2505021B2 (ja) 主記憶制御装置